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rev. 1.8 6/15 copyright ? 2015 by silicon laboratori es si8650/51/52/55 si8650/51/52/55 l ow p ower f ive -c hannel d igital i solator features applications safety regulatory approvals description silicon lab's family of ultra-low-power digital isolators are cmos devices offering substantial data rate, propagation delay, power, size, reliability, and external bom advantages over legacy isolation technologies. the operating parameters of these products remain stable across wide temperature ranges and throughout device service life for ease of design and highly uniform performance. all device versions have schmitt trigger inputs for high noise immunity and only require vdd bypass capacitors. data rates up to 150 mbps are supported, and all devices achieve propagation delays of less than 10 ns. enable inputs provide a single point control for enabling and disabling output drive. ordering options include a choice of isolation ratings (2.5, 3.75 and 5 kv) and a selectable fail-safe operating mode to control the default output stat e during power loss. all products >1 kv rms are safety certified by ul, csa, vde, and cqc, and products in wide-body packages support reinforced insulation withstanding up to 5 kv rms . ? high-speed operation ?? dc to 150 mbps ? no start-up initialization required ? wide operating supply voltage ?? 2.5?5.5 v ? up to 5000 v rms isolation ? 60-year life at rated working voltage ? high electromagnetic immunity ? ultra low power (typical) 5 v operation ?? 1.6 ma per channel at 1 mbps ?? 5.5 ma per channel at 100 mbps 2.5 v operation ?? 1.5 ma per channel at 1 mbps ?? 3.5 ma per channel at 100 mbps ? tri-state outputs with enable ? schmitt trigger inputs ? selectable fail-safe mode ?? default high or low output (ordering option) ? precise timing (typical) ?? 10 ns propagation delay ?? 1.5 ns pulse width distortion ?? 0.5 ns channel-channel skew ?? 2 ns propagation delay skew ?? 5 ns minimum pulse width ? transient immunity 50 kv/s ? aec-q100 qualification ? wide temperature range ?? ?40 to 125 c ? rohs-compliant packages ?? soic-16 wide body ?? soic-16 narrow body ?? qsop-16 ? industrial auto mation systems ? medical electronics ? hybrid electric vehicles ? isolated switch mode supplies ? isolated adc, dac ? motor control ? power inverters ? communication systems ? ul 1577 recognized ?? up to 5000 v rms for 1 minute ? csa component notice 5a approval ?? iec 60950-1, 61010-1, 60601-1 (reinforced insulation ) ? vde certification conformity ?? iec 60747-5-2 (vde0884 part 2) ?? en60950-1 (reinforced insulation) ? cqc certification approval ?? gb4943.1 ordering information: see page 30.
2 rev. 1.8 si8650/51/52/55
rev. 1.8 3 si8650/51/52/55 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 2.1. theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2. eye diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 3. device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1. device startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2. undervoltage lo ckout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3. layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4. fail-safe operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.5. typical performance char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4. pin descriptions (si8650/ 51/52) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5. pin descriptions (si8655) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7. package outline: 16-pin wide body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8. land pattern: 16-pin wide-b ody soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9. package outline: 16-pi n narrow body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10. land pattern: 16-pin narro w body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11. package outline: 16-pin qsop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 12. land pattern: 16-pin qsop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 13. top markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 13.1. top marking ( 16-pin wide body soic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 13.2. top marking explanati on (16-pin wide body soic ) . . . . . . . . . . . . . . . . . . . . . . . 40 13.3. top marking (16-pin na rrow body soic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 13.4. top marking explanati on (16-pin narrow body so ic) . . . . . . . . . . . . . . . . . . . . . . 41 13.5. top marking (16-pin qsop ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 13.6. top marking expl anation (16-pin qsop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4 rev. 1.8 si8650/51/52/55 1. electrical specifications table 1. recommended operating conditions parameter symbol min typ max unit ambient operating temperature* t a ?40 25 125 oc supply voltage v dd1 2.5 ? 5.5 v v dd2 2.5 ? 5.5 v *note: the maximum ambient temperature is dependent on data fre quency, output loading, number of operating channels, and supply voltage. table 2. electrical characteristics (v dd1 =5v10%, v dd2 =5v10%, t a = ?40 to 125 c) parameter symbol test condition min typ max unit vdd undervoltage threshold vdduv+ v dd1 , v dd2 rising 1.95 2.24 2.375 v vdd undervoltage threshold vdduv? v dd1 , v dd2 falling 1.88 2.16 2.325 v vdd undervoltage hysteresis vdd hys 50 70 95 mv positive-going input threshold vt+ all inputs rising 1.4 1.67 1.9 v negative-going input threshold vt? all inputs falling 1.0 1.23 1.4 v input hysteresis v hys 0.38 0.44 0.50 v high level input voltage v ih 2.0 ? ? v low level input voltage v il ??0.8v high level output voltage v oh loh = ?4 ma v dd1 ,v dd2 ?0.4 4.8 ? v low level output voltage v ol lol = 4 ma ? 0.2 0.4 v input leakage current i l ??10a output impedance 1 z o ?50? ? enable input high current i enh v enx =v ih ?2.0?a enable input low current i enl v enx =v il ?2.0?a notes: 1. the nominal output impedance of an isolat or driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and chan nel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, lo ad, and ambient temperature. 3. start-up time is the time period from the applic ation of power to valid data at the output.
rev. 1.8 5 si8650/51/52/55 dc supply current (all inputs 0 v or at supply) si8650bx, ex, si8655bx v dd1 v dd2 v dd1 v dd2 v i =0(bx), 1(ex) v i =0(bx), 1(ex) v i =1(bx), 0(ex) v i =1(bx), 0(ex) ? ? ? ? 1.1 3.1 7.0 3.3 1.8 4.7 9.8 5.0 ma si8651bx, ex v dd1 v dd2 v dd1 v dd2 v i =0(bx), 1(ex) v i =0(bx), 1(ex) v i =1(bx), 0(ex) v i =1(bx), 0(ex) ? ? ? ? 1.5 2.7 6.6 4.0 2.4 4.1 9.2 6.0 ma si8652bx, ex v dd1 v dd2 v dd1 v dd2 v i =0(bx), 1(ex) v i =0(bx), 1(ex) v i =1(bx), 0(ex) v i =1(bx), 0(ex) ? ? ? ? 2.0 2.4 5.6 5.0 3.0 3.6 7.8 7.5 ma 1 mbps supply current (all inputs = 500 khz square wave, ci = 15 pf on all outputs) si8650bx, ex, si8655bx v dd1 v dd2 ? ? 4.1 3.7 5.7 5.2 ma si8651bx, ex v dd1 v dd2 ? ? 4.2 3.8 5.8 5.3 ma si8652bx, ex v dd1 v dd2 ? ? 4.0 4.0 5.6 5.6 ma 10 mbps supply current (all inputs = 5 mhz square wave, ci = 15 pf on all outputs) si8650bx, ex, si8655bx v dd1 v dd2 ? ? 4.1 5.2 5.7 7.2 ma si8651bx, ex v dd1 v dd2 ? ? 4.4 4.9 6.2 6.9 ma si8652bx, ex v dd1 v dd2 ? ? 4.6 4.9 6.4 6.8 ma table 2. electrical characteristics (continued) (v dd1 =5v10%, v dd2 =5v10%, t a = ?40 to 125 c) parameter symbol test condition min typ max unit notes: 1. the nominal output impedance of an isolat or driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and chan nel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, lo ad, and ambient temperature. 3. start-up time is the time period from the applic ation of power to valid data at the output.
6 rev. 1.8 si8650/51/52/55 100 mbps supply current (all inputs = 50 mhz square wave, ci = 15 pf on all outputs) si8650bx, ex, si8655bx v dd1 v dd2 ? ? 4.1 22.1 5.7 28.7 ma si8651bx, ex v dd1 v dd2 ? ? 8.0 18.4 10.8 24 ma si8652bx, ex v dd1 v dd2 ? ? 11.7 15 15.2 19.5 ma timing characteristics si865xbx, ex maximum data rate 0 ? 150 mbps minimum pulse width ? ? 5.0 ns propagation delay t phl , t plh see figure 2 5.0 8.0 13 ns pulse width distortion |t plh ? t phl | pwd see figure 2 ? 0.2 4.5 ns propagation delay skew 2 t psk(p-p) ?2.04.5ns channel-channel skew t psk ?0.42.5ns all models output rise time t r c l =15pf see figure 2 ? 2.5 4.0 ns output fall time t f c l =15pf see figure 2 ? 2.5 4.0 ns peak eye diagram jitter t jit(pk) see figure 8 ? 350 ? ps common mode transient immunity cmti v i =v dd or 0 v v cm = 1500 v (see figure 3) 35 50 ? kv/s enable to data valid t en1 see figure 1 ? 6.0 11 ns enable to data tri-state t en2 see figure 1 ? 8.0 12 ns start-up time 3 t su ?1540s table 2. electrical characteristics (continued) (v dd1 =5v10%, v dd2 =5v10%, t a = ?40 to 125 c) parameter symbol test condition min typ max unit notes: 1. the nominal output impedance of an isolat or driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and chan nel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, lo ad, and ambient temperature. 3. start-up time is the time period from the applic ation of power to valid data at the output.
rev. 1.8 7 si8650/51/52/55 figure 1. enable timing diagram figure 2. propagation delay timing enable outputs t en1 t en2 typical input t plh t phl typical output t r t f 90% 10% 90% 10% 1.4 v 1.4 v
8 rev. 1.8 si8650/51/52/55 figure 3. common mode transient immunity test circuit oscilloscope 3 ? to ? 5 ? v isolated ? supply si86xx vdd2 output 3 ? to ? 5 ? v supply high voltage surge generator vcm ? surge output high voltage differential probe gnd2 gnd1 vdd1 input input ? signal switch input output isolated ? ground
rev. 1.8 9 si8650/51/52/55 table 3. electrical characteristics (v dd1 = 3.3 v10%, v dd2 = 3.3 v10%, t a = ?40 to 125 c) parameter symbol test condition min typ max unit vdd undervoltage threshold vdduv+ v dd1 , v dd2 rising 1.95 2.24 2.375 v vdd undervoltage threshold vdduv? v dd1 , v dd2 falling 1.88 2.16 2.325 v vdd undervoltage hysteresis vdd hys 50 70 95 mv positive-going input thresh- old vt+ all inputs rising 1.4 1.67 1.9 v negative-going input thresh- old vt? all inputs falling 1.0 1.23 1.4 v input hysteresis v hys 0.38 0.44 0.50 v high level input voltage v ih 2.0 ? ? v low level input voltage v il ??0.8v high level output voltage v oh loh = ?4 ma v dd1 ,v dd 2 ?0.4 3.1 ? v low level output voltage v ol lol = 4 ma ? 0.2 0.4 v input leakage current i l ??10a output impedance 1 z o ?50? ? enable input high current i enh v enx = v ih ?2.0?a enable input low current i enl v enx = v il ?2.0?a dc supply current (all inputs 0 v or at supply) si8650bx, ex, si8655bx v dd1 v dd2 v dd1 v dd2 v i = 0(bx), 1(ex) v i = 0(bx), 1(ex) v i = 1(bx), 0(ex) v i = 1(bx), 0(ex) ? ? ? ? 1.1 3.1 7.0 3.3 1.8 4.7 9.8 5.0 ma si8651bx, ex v dd1 v dd2 v dd1 v dd2 v i = 0(bx), 1(ex) v i = 0(bx), 1(ex) v i = 1(bx), 0(ex) v i = 1(bx), 0(ex) ? ? ? ? 1.5 2.7 6.6 4.0 2.4 4.1 9.2 6.0 ma si8652bx, ex v dd1 v dd2 v dd1 v dd2 v i = 0(bx), 1(ex) v i = 0(bx), 1(ex) v i = 1(bx), 0(ex) v i = 1(bx), 0(ex) ? ? ? ? 2.0 2.4 5.6 5.0 3.0 3.6 7.8 7.5 ma notes: 1. the nominal output impedance of an isol ator driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and chan nel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation de lay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. start-up time is the time period from the application of power to valid data at the output.
10 rev. 1.8 si8650/51/52/55 1 mbps supply current (all inputs = 500 khz square wave, ci = 15 pf on all outputs) si8650bx, ex, si8655bx v dd1 v dd2 ? ? 4.1 3.7 5.7 5.2 ma si8651bx, ex v dd1 v dd2 ? ? 4.2 3.8 5.8 5.3 ma si8652bx, ex v dd1 v dd2 ? ? 4.0 4.0 5.6 5.6 ma 10 mbps supply current (all inputs = 5 mhz square wave, ci = 15 pf on all outputs) si8650bx, ex, si8655bx v dd1 v dd2 ? ? 4.1 4.4 5.7 6.1 ma si8651bx, ex v dd1 v dd2 ? ? 4.3 4.3 6.0 6.0 ma si8652bx, ex v dd1 v dd2 ? ? 4.3 4.4 6.0 6.1 ma 100 mbps supply current (all inputs = 50 mhz square wave, ci = 15 pf on all outputs) si8650bx, ex, si8655bx v dd1 v dd2 ? ? 4.1 15.5 5.7 20.1 ma si8651bx, ex v dd1 v dd2 ? ? 6.6 13.2 8.9 17.1 ma si8652bx, ex v dd1 v dd2 ? ? 8.9 11.1 11.6 14.4 ma table 3. electrical characteristics (continued) (v dd1 = 3.3 v10%, v dd2 = 3.3 v10%, t a = ?40 to 125 c) parameter symbol test condition min typ max unit notes: 1. the nominal output impedance of an isol ator driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and chan nel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation de lay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. start-up time is the time period from the application of power to valid data at the output.
rev. 1.8 11 si8650/51/52/55 timing characteristics si865xbx, ex maximum data rate 0 ? 150 mbps minimum pulse width ? ? 5.0 ns propagation delay t phl , t plh see figure 2 5.0 8.0 13 ns pulse width distortion |t plh ? t phl | pwd see figure 2 ? 0.2 4.5 ns propagation delay skew 2 t psk(p-p) ?2.04.5ns channel-channel skew t psk ?0.42.5ns all models output rise time t r c l =15pf see figure 2 ? 2.5 4.0 ns output fall time t f c l =15pf (see figure 2) ? 2.5 4.0 ns peak eye diagram jitter t jit(pk) (see figure 8) ? 350 ? ps common mode transient immunity cmti v i =v dd or 0 v v cm = 1500 v (see figure 3) 35 50 ? kv/s enable to data valid t en1 see figure 1 ? 6.0 11 ns enable to data tri-state t en2 see figure 1 ? 8.0 12 ns start-up time 3 t su ?1540s table 3. electrical characteristics (continued) (v dd1 = 3.3 v10%, v dd2 = 3.3 v10%, t a = ?40 to 125 c) parameter symbol test condition min typ max unit notes: 1. the nominal output impedance of an isol ator driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and chan nel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation de lay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. start-up time is the time period from the application of power to valid data at the output.
12 rev. 1.8 si8650/51/52/55 table 4. electrical characteristics (v dd1 =2.5v 5%, v dd2 = 2.5 v 5%, t a = ?40 to 125 c) parameter symbol test condition min typ max unit vdd undervoltage threshold vdduv+ v dd1 , v dd2 rising 1.95 2.24 2.375 v vdd undervoltage threshold vdduv? v dd1 , v dd2 falling 1.88 2.16 2.325 v vdd undervoltage hysteresis vdd hys 50 70 95 mv positive-going input threshold vt+ all inputs rising 1.4 1.67 1.9 v negative-going input threshold v t? all inputs falling 1.0 1.23 1.4 v input hysteresis v hys 0.38 0.44 0.50 v high level input voltage v ih 2.0 ? ? v low level input voltage v il ??0.8v high level output voltage v oh loh = ?4 ma v dd1 ,v dd2 ?0.4 2.3 ? v low level output voltage v ol lol = 4 ma ? 0.2 0.4 v input leakage current i l ??10a output impedance 1 z o ?50? ? enable input high current i enh v enx =v ih ?2.0?a enable input low current i enl v enx =v il ?2.0?a dc supply current (all inputs 0 v or at supply) si8650bx, ex, si8655bx v dd1 v dd2 v dd1 v dd2 v i =0(bx), 1(ex) v i =0(bx), 1(ex) v i =1(bx), 0(ex) v i =1(bx), 0(ex) ? ? ? ? 1.1 3.1 7.0 3.3 1.8 4.7 9.8 5.0 ma si8651bx, ex v dd1 v dd2 v dd1 v dd2 v i =0(bx), 1(ex) v i =0(bx), 1(ex) v i =1(bx), 0(ex) v i =1(bx), 0(ex) ? ? ? ? 1.5 2.7 6.6 4.0 2.4 4.1 9.2 6.0 ma si8652bx, ex v dd1 v dd2 v dd1 v dd2 v i =0(bx), 1(ex) v i =0(bx), 1(ex) v i =1(bx), 0(ex) v i =1(bx), 0(ex) ? ? ? ? 2.0 2.4 5.6 5.0 3.0 3.6 7.8 7.5 ma notes: 1. the nominal output impedance of an isolat or driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and c hannel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. start-up time is the time period from the application of power to valid data at the output.
rev. 1.8 13 si8650/51/52/55 1 mbps supply current (all inputs = 500 khz square wave, ci = 15 pf on all outputs) si8650bx, ex, si8655bx v dd1 v dd2 ? ? 4.1 3.7 5.7 5.2 ma si8651bx, ex v dd1 v dd2 ? ? 4.2 3.8 5.8 5.3 ma si8652bx, ex v dd1 v dd2 ? ? 4.0 4.0 5.6 5.6 ma 10 mbps supply current (all inputs = 5 mhz square wave, ci = 15 pf on all outputs) si8650bx, ex, si8655bx v dd1 v dd2 ? ? 4.1 4.0 5.7 5.6 ma si8651bx, ex v dd1 v dd2 ? ? 4.2 4.0 5.9 5.6 ma si8652bx, ex v dd1 v dd2 ? ? 4.1 4.2 5.8 5.9 ma 100 mbps supply current (all inputs = 50 mhz square wave, ci = 15 pf on all outputs) si8650bx, ex, si8655bx v dd1 v dd2 ? ? 4.1 12.5 5.7 16.2 ma si8651bx, ex v dd1 v dd2 ? ? 6.0 10.8 8.1 14 ma si8652bx, ex v dd1 v dd2 ? ? 7.6 9.3 9.9 12.0 ma table 4. electrical characteristics (continued) (v dd1 =2.5v 5%, v dd2 = 2.5 v 5%, t a = ?40 to 125 c) parameter symbol test condition min typ max unit notes: 1. the nominal output impedance of an isolat or driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and c hannel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. start-up time is the time period from the application of power to valid data at the output.
14 rev. 1.8 si8650/51/52/55 timing characteristics si865xbx, ex maximum data rate 0?150 mbps minimum pulse width ??5.0 ns propagation delay t phl , t plh see figure 2 5.0 8.0 14 ns pulse width distortion |t plh - t phl | pwd see figure 2 ?0.25.0 ns propagation delay skew 2 t psk(p-p) ?2.05.0 ns channel-channel skew t psk ?0.42.5 ns all models output rise time t r c l =15pf see figure 2 ? 2.5 4.0 ns output fall time t f c l =15pf see figure 2 ? 2.5 4.0 ns peak eye diagram jitter t jit(pk) see figure 8 ? 350 ? ps common mode transient immunity cmti v i =v dd or 0 v v cm =1500v (see figure 3) 35 50 ?kv/s enable to data valid t en1 see figure 1 ? 6.0 11 ns enable to data tri-state t en2 see figure 1 ? 8.0 12 ns startup time 3 t su ?1540s table 4. electrical characteristics (continued) (v dd1 =2.5v 5%, v dd2 = 2.5 v 5%, t a = ?40 to 125 c) parameter symbol test condition min typ max unit notes: 1. the nominal output impedance of an isolat or driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and c hannel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. start-up time is the time period from the application of power to valid data at the output.
rev. 1.8 15 si8650/51/52/55 table 5. regulatory information* csa the si865x is certified under csa component acceptanc e notice 5a. for more details, see file 232873. 61010-1: up to 600 v rms reinforced insulation working voltage; up to 600 v rms basic insulation working voltage. 60950-1: up to 600 v rms reinforced insulation working voltage; up to 1000 v rms basic insulation working volt- age. 60601-1: up to 125 v rms reinforced insulation working voltage; up to 380 v rms basic insulation working voltage. vde the si865x is certified according to iec 60747-5-2. for more details, see file 5006301-4880-0001. 60747-5-2: up to 1200 v peak for basic insulation working voltage. 60950-1: up to 600 v rms reinforced insulation working voltage; up to 1000 v rms basic insulation working volt- age. ul the si865x is certified under ul15 77 component recognition program. for more details, see file e257455. rated up to 5000 v rms isolation voltage for basic protection. cqc the si865x is certified under gb49 43.1-2011. for more details, see certificates cqc13001096110 and cqc13001096239. rated up to 600 v rms reinforced insulation wo rking voltage; up to 1000 v rms basic insulation working voltage. *note: regulatory certifications apply to 2.5 kv rms rated devices which are production tested to 3.0 kv rms for 1 sec. regulatory certificat ions apply to 3.75 kv rms rated devices which are production tested to 4.5 kv rms for 1 sec. regulatory certificat ions apply to 5.0 kv rms rated devices which are production tested to 6.0 kv rms for 1 sec. for more information, see "6. ordering guide" on page 30.
16 rev. 1.8 si8650/51/52/55 table 6. insulation and safety-related specifications parameter symbol test condition value unit wb soic-16 nb soic-16 qsop-16 nominal air gap (clearance) 1 l(io1) 8.0 4.9 3.6 mm nominal external tracking (creepage) 1 l(io2) 8.0 4.01 3.6 mm minimum internal gap (internal clearance) 0.014 0.014 0.014 mm tracking resistance (proof tracking index) pti iec60112 600 600 600 v rms erosion depth ed 0.019 0.019 0.031 mm resistance (input-output) 2 r io 10 12 10 12 10 12 ? capacitance (input-output) 2 c io f = 1 mhz 2.0 2.0 2.0 pf input capacitance 3 c i 4.0 4.0 4.0 pf notes: 1. the values in this table correspond to the nominal creep age and clearance values. vde certifies the clearance and creepage limits as 4.7 mm minimum for the nb soic-16 and qsop-16 packages and 8.5 mm minimum for the wb soic-16 package. ul does not impose a clearance and cr eepage minimum for component-level certifications. csa certifies the clearance and creepage limits as 3.9 mm minimum for the nb soic-16, 3.6 mm minimum for the qsop- 16 packages and 7.6 mm minimum for the wb soic-16 package. 2. to determine resistance and capacitance, the si86xx is co nverted into a 2-terminal device. pins 1?8 are shorted together to form the first terminal and pins 9?16 are short ed together to form the second terminal. the parameters are then measured between these two terminals. 3. measured from input pin to ground. table 7. iec 60664-1 (vde 0844 part 2) ratings parameter test conditions specification nb soic-16 wb soic-16 basic isolation group material group i i installation classification rated mains voltages < 150 v rms i-iv i-iv rated mains voltages < 300 v rms i-iii i-iv rated mains voltages < 400 v rms i-ii i-iii rated mains voltages < 600 v rms i-ii i-iii
rev. 1.8 17 si8650/51/52/55 table 8. iec 60747-5-2 insulation characteristics for si86xxxx* parameter symbol test condition characteristic unit wb soic-16 nb soic-16 maximum working insulation voltage v iorm 1200 630 vpeak input to output test voltage v pr method b1 (v iorm x1.875=v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc) 2250 1182 transient overvoltage v iotm t = 60 sec 6000 6000 vpeak pollution degree (din vde 0110, table 1) 22 insulation resistance at t s , v io =500v r s >10 9 >10 9 ? *note: maintenance of the safety data is ensured by protective circuits. the si86xxxx provides a climate classification of 40/125/21. table 9. iec safety limiting values 1 parameter symbol test condition max unit wb soic-16 nb soic-16 case temperature t s 150 150 c safety input, output, or supply current i s ? ja = 100 c/w (wb soic-16), 105 c/w (nb soic-16, qsop-16), v i =5.5v, t j =150c, t a =25c 220 215 ma device power dissipation 2 p d 415 415 mw notes: 1. maximum value allowed in the event of a failure; al so see the thermal derating curve in figures 4 and 5. 2. the si86xx is tested with vdd1 = vdd2 = 5.5 v, t j =150oc, c l = 15 pf, input a 150 mbps 50% duty cycle square wave.
18 rev. 1.8 si8650/51/52/55 figure 4. (wb soic-16) thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 figure 5. (nb soic-16) thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 table 10. thermal characteristics parameter symbol wb soic-16 nb soic-16 qsop-16 unit ic junction-to-air thermal resistance ? ja 100 105 oc/w 0 200 150 100 50 500 400 200 100 0 temperature (oc) safety-limiting current (ma) 450 300 370 220 v dd1 , v dd2 = 2.70 v v dd1 , v dd2 = 3.6 v v dd1 , v dd2 = 5.5 v 0 200 150 100 50 500 400 200 100 0 temperature (oc) safety-limiting current (ma) 430 300 360 215 v dd1 , v dd2 = 2.70 v v dd1 , v dd2 = 3.6 v v dd1 , v dd2 = 5.5 v
rev. 1.8 19 si8650/51/52/55 table 11. absolute maximum ratings 1 parameter symbol min max unit storage temperature 2 t stg ?65 150 c ambient temperature under bias t a ?40 125 c junction temperature t j ? 150 c supply voltage v dd1 , v dd2 ?0.5 7.0 v input voltage v i ?0.5 v dd + 0.5 v output voltage v o ?0.5 v dd + 0.5 v output current drive channel (all devices unless otherwise stated) i o ?10ma output current drive channel (all si865xxa-x-xx devices) i o ?22ma latchup immunity 3 ? 100 v/ns lead solder temperature (10 s) ? 260 c maximum isolation (input to output) (1 sec) nb soic-16, qsop-16 ?4500v rms maximum isolation (input to output) (1 sec) wb soic-16 ?6500v rms notes: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to conditions as specified in the operational sections of this data sheet. 2. vde certifies storage temperature from ?40 to 150 c. 3. latchup immunity specification is for slew rate applied across gnd1 and gnd2.
20 rev. 1.8 si8650/51/52/55 2. functional description 2.1. theory of operation the operation of an si865x channel is analogous to that of an opto coupler, except an rf carrier is modulated instead of light. this simple archit ecture provides a robust isolated data path and requires no special considerations or initialization at start-up. a simplified block diagram for a single si865x channel is shown in figure 6. figure 6. simplified channel diagram a channel consists of an rf transmitter and rf receiver separated by a semiconductor-based isolation barrier. referring to the transmitter, input a modulates the carrier provided by an rf oscillator using on/off keying. the receiver contains a demodulator that decodes the input state according to its rf energy content and applies the result to output b via the output driv er. this rf on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consum ption, and better immunity to magnetic fields. see figure 7 for more details. figure 7. modulation scheme rf oscillator modulator demodulator a b semiconductor- based isolation barrier transmitter receiver input signal output signal modulation signal
rev. 1.8 21 si8650/51/52/55 2.2. eye diagram figure 8 illustrates an eye-diagram take n on an si8650. for the data source, the test used an anritsu (mp1763c) pulse pattern generator set to 1000 ns/div. the output of the generator's clock and data from an si8650 were captured on an oscillosc ope. the results illustra te that data integrity was mainta ined even at the high data rate of 150 mbps. the results also show that 2 ns pulse wid th distortion and 350 ps peak jitter were exhibited. figure 8. eye diagram
22 rev. 1.8 si8650/51/52/55 3. device operation device behavior during start-up, normal operation, an d shutdown is shown in figu re 9, where uvlo+ and uvlo- are the positive-going and negative-going thresholds resp ectively. refer to table 12 to determine outputs when power supply (vdd) is not present. additionally, refer to table 13 for logic conditions when enable pins are used. table 12. si865x logic operation v i input 1,2 en input 1,2,3,4 vddi state 1,5,6 vddo state 1,5,6 v o output 1,2 comments h h or nc p p h enabled, normal operation. lh or nc p p l x 7 l p p hi-z 8 disabled. x 7 h or nc up p l 9 h 9 upon transition of vddi from unpowered to pow- ered, v o returns to the same state as v i in less than 1 s. x 7 l up p hi-z 8 disabled. x 7 x 7 p up undetermined upon transition of vddo from unpowered to pow- ered, v o returns to the same state as v i within 1 s, if en is in either th e h or nc state. upon tran- sition of vddo from unpowered to powered, v o returns to hi-z within 1 s if en is l. notes: 1. vddi and vddo are the input and output power supplies. v i and v o are the respective input and output terminals. en is the enable control input located on the same output side. 2. x = not applicable; h = logic high; l = logic low; hi-z = high impedance. 3. it is recommended that the enable inputs be connected to an external logic high or low level when the si865x is operating in noisy environments. 4. no connect (nc) replaces en1 on si8650. no connects are no t internally connected and can be left floating, tied to vdd, or tied to gnd. 5. ?powered? state (p) is defined as 2.5 v < vdd < 5.5 v. 6. ?unpowered? state (up) is defined as vdd = 0 v. 7. note that an i/o can power the die for a given side through an internal diode if its source has adequate current. 8. when using the enable pin (en) function, the output pin state is driven into a high-impedance state when the en pin is disabled (en = 0). 9. see "6. ordering guide" on page 30 for details. this is the selectable fail-safe operating mode (ordering option). some devices have default output state = h, and some have default output state = l, depending on the ordering part number (opn). for default high devices, the data channels have pull-ups on inputs/outputs. for default low devices, the data channels have pull-downs on inputs/outputs.
rev. 1.8 23 si8650/51/52/55 table 13. enable input truth 1 p/n en1 1,2 en2 1,2 operation si8650 ? h outputs b1, b2, b3, b4, b5 are enabled and follow input state. ? l outputs b1, b2, b3, b4, b5 are disabled and logic low or in high impedance state. 3 si8651 h x output a5 enabled and follow input state. l x output a5 disabled and in high impedance state. 3 x h outputs b1, b2, b3, b4 are enabled and follow input state. x l outputs b1, b2, b3, b4 are disabled and in high impedance state. 3 si8652 h x outputs a4 and a5 are enabled and follow input state. l x outputs a4 and a5 are disabled and in high impedance state. 3 x h outputs b1, b2, b3 are enabled and follow input state. x l outputs b1, b2, b3 are disabled and in high impedance state. 3 si8655 ? ? outputs b1, b2, b3, b4, b5 are enabled and follow input state. notes: 1. enable inputs en1 and en2 can be used for multiplexing, for clock sync, or other output control. these inputs are internally pulled-up to local vdd by a 2 a current source allowing them to be connected to an external logic level (high or low) or left floating. to minimize noise coupling, do not c onnect circuit traces to en1 or en2 if they are left floating. if en1, en2 are unused, it is recommended they be connected to an external logic level, especially if the si865x is operating in a noisy environment. 2. x = not applicable; h = logic high; l = logic low. 3. when using the enable pin (en) function, the output pin state is driven into a high-impedance state when the en pin is disabled (en = 0).
24 rev. 1.8 si8650/51/52/55 3.1. device startup outputs are held low during powerup until vdd is above the uvlo threshold for time period tstart. following this, the outputs follow the states of inputs. 3.2. undervoltage lockout undervoltage lockout (uvlo) is provided to prevent erroneous operation during device startup and shutdown or when vdd is below its specified operating circuits range. both side a and side b each have their own undervoltage lockout monitors. each side can enter or exit uvlo independently. for example, side a unconditionally enters uvlo when v dd1 falls below v dd1(uvlo?) and exits uvlo when v dd1 rises above v dd1(uvlo+) . side b operates the same as side a with respect to its v dd2 supply. figure 9. device behavior during normal operation input v dd1 uvlo- v dd2 uvlo+ uvlo- uvlo+ output tstart tstart tstart tphl tplh tsd
rev. 1.8 25 si8650/51/52/55 3.3. layout recommendations to ensure safety in the end us er application, high voltage circ uits (i.e., circuits with >30 v ac ) must be physically separated from the safety extra-low voltage circuits (selv is a circuit with <30 v ac ) by a certain distance (creepage/clearance). if a component, su ch as a digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating (commonly referred to as working voltage protection). table 5 on page 15 and table 6 on page 16 detail the working voltage and creepage/clearan ce capabilities of the si86xx. thes e tables also detail the component standards (ul1577, iec60747, csa 5a), which are readily accepted by certif ication bodies to provide proof for end-system specifications requirements. refer to the en d-system specification (61010-1, 60950-1, 60601-1, etc.) requirements before starting any design that uses a digital isolator. 3.3.1. supply bypass the si865x family requires a 0.1 f bypass capacitor between v dd1 and gnd1 and v dd2 and gnd2. the capacitor should be placed as close as possible to the package. to enhance the robustness of a design, the user may also include resistors (50?300 ? ) in series with the inputs and outp uts if the system is excessively noisy. 3.3.2. output pin termination the nominal output impedance of an isolat or driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series term ination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appr opriately terminated with controlled impedance pcb traces. 3.4. fail-saf e operating mode si86xx devices feature a selectable (by ordering option ) mode whereby the default ou tput state (when the input supply is unpowered) can either be a logic high or logi c low when the output supply is powered. see table 12 on page 22 and "6. ordering guide" on page 30 for more information.
26 rev. 1.8 si8650/51/52/55 3.5. typical perfor mance characteristics the typical performance characteristics de picted in the following diagrams are for information purposes only. refer to tables 2, 3, and 4 for actual specification limits. figure 10. si8650/55 typical v dd1 supply current vs. data rate 5, 3.3, and 2.5 v operation figure 11. si8651 typical v dd1 supply current vs. data rate 5, 3.3, and 2.5 v operation (15 pf load) figure 12. si8652 typical v dd1 supply current vs. data rate 5, 3.3, and 2.5 v operation (15 pf load) figure 13. si8650/55 typical v dd2 supply current vs. data rate 5, 3.3, and 2.5 v operation (15 pf load) figure 14. si8651 typical v dd2 supply current vs. data rate 5, 3.3, and 2.5 v operation (15 pf load) figure 15. si8652 typical v dd2 supply current vs. data rate 5, 3.3, and 2.5 v operation (15 pf load) 0.0 5.0 10.0 15.0 20.0 25.0 30.0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 current (ma) data rate (mbps) 5v 3.3v 2.5v 0.0 5.0 10.0 15.0 20.0 25.0 30.0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 current (ma) data rate (mbps) 5v 3.3v 2.5v 0.0 5.0 10.0 15.0 20.0 25.0 30.0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 current (ma) data rate (mbps) 5v 3.3v 2.5v 0.0 5.0 10.0 15.0 20.0 25.0 30.0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 current (ma) data rate (mbps) 5v 3.3v 2.5v 0.0 5.0 10.0 15.0 20.0 25.0 30.0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 current (ma) data rate (mbps) 5v 3.3v 2.5v 0.0 5.0 10.0 15.0 20.0 25.0 30.0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 current (ma) data rate (mbps) 5v 3.3v 2.5v
rev. 1.8 27 si8650/51/52/55 figure 16. propagation delay vs. temperature 5.0 6.0 7.0 8.0 9.0 10.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100110120 delay (ns) temperature (degrees c)
28 rev. 1.8 si8650/51/52/55 4. pin descriptions (si8650/51/52) name soic-16 pin# type description v dd1 1 supply side 1 power supply. a1 2 digital input side 1 digital input. a2 3 digital input side 1 digital input. a3 4 digital input side 1 digital input. a4 5 digital i/o side 1 digital input or output. a5 6 digital i/o side 1 digital input or output. en1/nc* 7 digital input side 1 active high enable. nc on si8650. gnd1 8 ground side 1 ground. gnd2 9 ground side 2 ground. en2 10 digital input side 2 active high enable. b5 11 digital i/o side 2 digital input or output. b4 12 digital i/o side 2 digital input or output. b3 13 digital output side 2 digital output. b2 14 digital output side 2 digital output. b1 15 digital output side 2 digital output. v dd2 16 supply side 2 power supply. *note: no connect. these pins are not internally con nected. they can be left floating, tied to v dd or tied to gnd. v dd1 a1 a3 a4 nc gnd1 a2 v dd2 b2 b1 b4 b3 gnd2 en2/nc i s o l a t i o n rf xmitr rf rcvr rf xmitr rf rcvr rf xmitr rf rcvr rf xmitr rf rcvr si8650 a5 rf xmitr rf rcvr b5 v dd1 a1 a3 a4 en1 gnd1 a2 v dd2 b2 b1 b4 b3 gnd2 en2 i s o l a t i o n rf xmitr rf rcvr rf xmitr rf rcvr rf xmitr rf rcvr rf xmitr rf rcvr si8651 rf xmitr rf rcvr a5 b5 v dd1 a1 a3 a4 en1 gnd1 a2 v dd2 b2 b1 b4 b3 gnd2 en2 i s o l a t i o n rf xmitr rf rcvr rf xmitr rf rcvr rf rcvr rf xmitr rf rcvr rf xmitr rf rcvr si8652 rf xmitr rf rcvr a5 b5 v dd1 a1 a3 a4 en1 gnd1 a2 v dd2 b2 b1 b4 b3 gnd2 en2 i s o l a t i o n rf xmitr rf rcvr rf xmitr rf rcvr rf xmitr rf rcvr rf xmitr rf rcvr si8651 rf xmitr rf rcvr a5 b5
rev. 1.8 29 si8650/51/52/55 5. pin descriptions (si8655) name soic-16 pin# type description v dd1 1 supply side 1 power supply. gnd1 2* ground side 1 ground. a1 3 digital input side 1 digital input. a2 4 digital input side 1 digital input. a3 5 digital input side 1 digital input. a4 6 digital input side 1 digital input. a5 7 digital input side 1 digital input. gnd1 8* ground side 1 ground. gnd2 9* ground side 2 ground. b5 10 digital output side 2 digital output. b4 11 digital output side 2 digital output. b3 12 digital output side 2 digital output. b2 13 digital output side 2 digital output. b1 14 digital output side 2 digital output. gnd2 15* ground side 2 ground. v dd2 16 supply side 2 power supply. *note: for narrow-body devices, pin 2 and pin 8 gnd must be exte rnally connected to respective ground. pin 9 and pin 15 must also be connected to external ground. v dd1 a1 a3 a4 gnd1 a2 v dd2 b2 b1 b4 b3 gnd2 i s o l a t i o n rf xmitr rf rcvr rf xmitr rf rcvr rf xmitr rf rcvr rf xmitr rf rcvr si8655 a5 rf xmitr rf rcvr b5 gnd1 gnd2
30 rev. 1.8 si8650/51/52/55 6. ordering guide table 14. ordering guide for valid opns 1,2 ordering part number (opn) number of inputs vdd1 side number of inputs vdd2 side max data rate (mbps) default output state isolation rating (kv) temp (c) package si8650bb-b-is1 5 0 150 low 2.5 ?40 to 125 c nb soic-16 si8650ec-b-is1 5 0 150 high 3.75 ?40 to 125 c nb soic-16 si8650bd-b-is 5 0 150 low 5.0 ?40 to 125 c wb soic-16 si8650ed-b-is 5 0 150 high 5.0 ?40 to 125 c wb soic-16 si8651bb-b-is1 4 1 150 low 2.5 ?40 to 125 c nb soic-16 si8651bc-b-is1 4 1 150 low 3.75 ?40 to 125 c nb soic-16 si8651ec-b-is1 4 1 150 high 3.75 ?40 to 125 c nb soic-16 si8651bd-b-is 4 1 150 low 5.0 ?40 to 125 c wb soic-16 si8651ed-b-is 4 1 150 high 5.0 ?40 to 125 c wb soic-16 SI8652BB-B-IS1 3 2 150 low 2.5 ?40 to 125 c nb soic-16 si8652bc-b-is1 3 2 150 low 3.75 ?40 to 125 c nb soic-16 si8652ec-b-is1 3 2 150 high 3.75 ?40 to 125 c nb soic-16 si8652bd-b-is 3 2 150 low 5.0 ?40 to 125 c wb soic-16 si8652ed-b-is 3 2 150 high 5.0 ?40 to 125 c wb soic-16 si8655ba-b-iu 5 0 150 low 1.0 ?40 to 125 c qsop-16 si8655ba-c-iu 5 0 150 low 1.0 ?40 to 125 c qsop-16 si8655ba-b-is 5 0 150 low 1.0 ?40 to 125 c wb soic-16 si8655bb-b-is1 5 0 150 low 2.5 ?40 to 125 c nb soic-16 si8655bd-b-is 5 0 150 low 5.0 ?40 to 125 c wb soic-16 notes: 1. all packages are rohs-compliant with peak reflow temperat ures of 260 c according to the jedec industry standard classifications and peak solder temperatures. 2. ?si? and ?si? are used interchangeably.
rev. 1.8 31 si8650/51/52/55 7. package outline: 16-pin wide body soic figure 17 illustrates the package details for the si865x digital isolator. ta ble 15 lists the values for the dimensions shown in the illustration. figure 17. 16-pin wide body soic
32 rev. 1.8 si8650/51/52/55 table 15. package diagram dimensions dimension min max a ? 2.65 a1 0.10 0.30 a2 2.05 ? b 0.31 0.51 c 0.20 0.33 d 10.30 bsc e 10.30 bsc e1 7.50 bsc e 1.27 bsc l 0.40 1.27 h 0.25 0.75 ? 0 8 aaa ?0.10 bbb ? 0.33 ccc ? 0.10 ddd ? 0.25 eee ? 0.10 fff ? 0.20 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jede c outline ms-013, variation aa. 4. recommended reflow profile per jedec j-std-020c specification for small body, lead-free components.
rev. 1.8 33 si8650/51/52/55 8. land pattern: 16-pin wide-body soic figure 18 illustrates the reco mmended land pattern details for the si865x in a 16-p in wide-body soic. table 16 lists the values for the dimens ions shown in the illustration. figure 18. 16-pin soic land pattern table 16. 16-pin wide body soic land pattern dimensions dimension feature (mm) c1 pad column spacing 9.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.90 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p1032x265-16an for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed.
34 rev. 1.8 si8650/51/52/55 9. package outline: 16 -pin narrow body soic figure 19 illustrates the package details for the si865x in a 16-pin narrow-body soic (so-16). table 17 lists the values for the di mensions shown in the illustration. figure 19. 16-pin small outline integrated circuit (soic) package
rev. 1.8 35 si8650/51/52/55 table 17. package diagram dimensions dimension min max a ? 1.75 a1 0.10 0.25 a2 1.25 ? b 0.31 0.51 c 0.17 0.25 d9.90 bsc e6.00 bsc e1 3.90 bsc e1.27 bsc l 0.40 1.27 l2 0.25 bsc h 0.25 0.50 0 8 aaa 0.10 bbb 0.20 ccc 0.10 ddd 0.25 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline ms-012, variation ac. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
36 rev. 1.8 si8650/51/52/55 10. land pattern: 1 6-pin narrow body soic figure 20 illustrates the recommended land pattern details for the si865x in a 16-pin narrow-body soic. table 18 lists the values for the dimens ions shown in the illustration. figure 20. 16-pin narrow body soic pcb land pattern table 18. 16-pin narrow body soic land pattern dimensions dimension feature (mm) c1 pad column spacing 5.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.55 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p600x165-16n for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed.
rev. 1.8 37 si8650/51/52/55 11. package outline: 16-pin qsop figure 21 illustrates the package details for the si865 x in a 16-pin qsop package. ta ble 19 lists the values for the dimensions shown in the illustration. figure 21. 16-pin qsop package ?
38 rev. 1.8 si8650/51/52/55 table 19. package diagram dimensions dimension min max a ? 1.75 a1 0.10 0.25 a2 1.25 ? b 0.20 0.30 c 0.17 0.25 d 4.89 bsc e 6.00 bsc e1 3.90 bsc e 0.635 bsc l 0.40 1.27 l2 0.25 bsc h 0.25 0.50 0 8 aaa 0.10 bbb 0.20 ccc 0.10 ddd 0.25 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-137, variation ab. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
rev. 1.8 39 si8650/51/52/55 12. land pattern: 16-pin qsop figure 22 illustrates the recommended land pattern details for the si865x in a 16-pin narrow-body soic. table 20 lists the values for the dimens ions shown in the illustration. figure 22. 16-pin qsop pcb land pattern table 20. 16-pin qsop land pattern dimensions dimension feature (mm) c1 pad column spacing 5.40 e pad row pitch 0.635 x1 pad width 0.40 y1 pad length 1.55 notes: 1. this land pattern design is based on ipc-7351 pattern sop63p602x173-16n for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed. ?
40 rev. 1.8 si8650/51/52/55 13. top markings 13.1. top marking (16-pin wide body soic) 13.2. top marking explanatio n (16-pin wide body soic) line 1 marking: base part number ordering options (see ordering guide for more information). si86 = isolator product series xy = channel configuration x = # of data channels (5, 4, 3, 2, 1) y = # of reverse channels (2, 1, 0)* s = speed grade (max data rate) and operating mode: a = 1 mbps (default output = low) b = 150 mbps (default output = low) d = 1 mbps (default output = high) e = 150 mbps (default output = high) v = insulation rating a = 1 kv; b = 2.5 kv; c = 3.75 kv; d = 5.0 kv line 2 marking: yy = year ww = workweek assigned by assembly subcontractor. corresponds to the year and work week of the mold date. rttttt = mfg code manufacturing code from assembly house ?r? indicates revision line 3 marking: circle = 1.7 mm diameter (center-justified) ?e4? pb-free symbol country of origin iso code abbreviation tw = taiwan *note: si8655 has 0 reverse channels. si86xysv yywwrttttt tw e4
rev. 1.8 41 si8650/51/52/55 13.3. top marking (16-pin narrow body soic) 13.4. top marking explanatio n (16-pin narrow body soic) line 1 marking: base part number ordering options (see ordering guide for more information). si86 = isolator product series xy = channel configuration x = # of data channels (5, 4, 3, 2, 1) y = # of reverse channels (2, 1, 0)* s = speed grade (max data rate) and operating mode: a = 1 mbps (default output = low) b = 150 mbps (default output = low) d = 1 mbps (default output = high) e = 150 mbps (default output = high) v = insulation rating a = 1 kv; b = 2.5 kv; c = 3.75 kv line 2 marking: circle = 1.2 mm diameter ?e3? pb-free symbol yy = year ww = work week assigned by the assembly subcontractor. corresponds to the year and work week of the mold date. rttttt = mfg code manufacturing code from assembly house ?r? indicates revision *note: si8655 has 0 reverse channels. si86xysv yywwrttttt e3
42 rev. 1.8 si8650/51/52/55 13.5. top marking (16-pin qsop) 13.6. top marking expl anation (16-pin qsop) line 1 marking: base part number ordering options (see ordering guide for more information). 86 = isolator product series xy = channel configuration x = # of data channels (5, 4, 3, 2, 1) y = # of reverse channels (2, 1, 0)* s = speed grade (max data rate) and operating mode: a = 1 mbps (default output = low) b = 150 mbps (default output = low) d = 1 mbps (default output = high) e = 150 mbps (default output = high) v = insulation rating a=1kv; b=2.5kv; c=3.75kv line 2 marking: rttttt = mfg code manufacturing code from assembly house ?r? indicates revision line 3 marking: yy = year ww = work week assigned by the assembly hous e. corresponds to the year and work week of the mold date. *note: si8655 has 0 reverse channels.
rev. 1.8 43 si8650/51/52/55 d ocument c hange l ist revision 0.1 to revision 0.2 ? deleted sections 4.3.4 and 4.3.5. ? updated "6. ordering guide" on page 30. ?? updated table 14, ?ordering guide for valid opns 1 , 2 ,? on page 30. ? added "3.4. fail-safe operating mode" on page 25. revision 0.2 to revision 1.0 ? added chip graphics on page 1. ? moved tables 1 and 11 to page 19. ? updated table 6, ?insulation and safety-related specifications,? on page 16. ? updated table 8, ?iec 60747-5-2 insulation characteristics for si86xxxx*,? on page 17. ? moved table 12 to page 22. ? moved table 13 to page 23. ? moved ?typical performance characteristics? to page 26. ? updated "4. pin descriptions (si8650/51/52)" on page 28. ? updated "5. pin descriptions (si8655)" on page 29. ? updated "6. ordering guide" on page 30. revision 1.0 to revision 1.1 ? reordered spec tables to conform to new convention. ? removed ?pending? throughout document. revision 1.1 to revision 1.2 ? updated high level output voltage voh to 3.1 v in table 3, ?electrical characteristics,? on page 9. ? updated high level output voltage voh to 2.3 v in table 4, ?electrical characteristics,? on page 12. revision 1.2 to revision 1.3 ? added output curr ent drive channel specification for si865xxa-x-xx devices. ? added latchup immunity specification. revision 1.3 to revision 1.4 ? updated table 14, ?ordering guide for valid opns 1 , 2 ,? on page 30. ?? updated note 1 with msl2a. revision 1.4 to revision 1.5 ? updated "6. ordering guide" on page 30 to include msl2a. ? updated table 14, ?ordering guide for valid opns 1 , 2 ,? on page 30. revision 1.5 to revision 1.6 ? updated table 11 on page 19. ?? added junction temperature spec. ? updated "3.3.1. supply bypass" on page 25. ? removed ?3.3.2. pin connections? on page 23. ? updated "4. pin descriptions (si8650/51/52)" on page 28. ?? updated table notes. ? updated "6. ordering guide" on page 30. ?? removed rev a devices. ? updated "7. package outline: 16-pin wide body soic" on page 31. ? updated top marks. ?? added revision description. revision 1.6 to revision 1.7 ? added figure 3, ?common mode transient immunity test circuit,? on page 8. ? added references to cqc throughout. ? added references to 2.5 kv rms devices throughout. ? updated "6. ordering guide" on page 30. ? updated "13.1. top marking (16-pin wide body soic)" on page 40. ? updated "13.5. top marking (16-pin qsop)" on page 42. revision 1.7 to revision 1.8 ? updated table 5 on page 15. ?? added cqc certificate numbers. ? updated "6. ordering guide" on page 30. ?? removed references to moisture sensitivity levels. ?? removed note 2.
44 rev. 1.8 si8650/51/52/55 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. patent notice silicon labs invests in research and development to help our cust omers differentiate in the market with innovative low-power, s mall size, analog- intensive mixed-signal soluti ons. silicon labs' extensive pat ent portfolio is a testament to our unique approach and world-clas s engineering team. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibilit y for errors and omissions, and disclaims responsibilit y for any consequences resu lting from the use of information included herein. ad ditionally, silicon laboratories assumes no re sponsibility for the functioning of und escribed fea- tures or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no warranty, representation or guarantee regarding the suitability of its pr oducts for any particular purpose, nor does silicon laboratories assume any liability arising out of the application or use of any product or circuit, and specific ally disclaims any and all liability, in cluding without limitation consequential or incidental damages. silicon laboratories products are not designed, int ended, or authorized for use in applica tions intend- ed to support or sustain life, or for any other application in which the failure of the silic on laboratories product could crea te a situation where personal injury or death may occur. should buyer purchase or use silicon laboratories products for any such unintended or unaut horized application, buyer sha ll indemnify and hold silicon laboratories harmless against all claims and damages.

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